1. Field of the Invention
The present invention relates to a method for manufacturing semiconductor devices having a dual damascene structure, and in particular to a method for manufacturing semiconductor devices having a dual damascene structure with high dimension precision.
2. Description of the Related Art
When forming a wiring layer in typical conventional methods for manufacturing semiconductor devices, a wiring metal layer is formed on the entire surface of a semiconductor substrate and thereafter a photoresist having the shape of a wiring pattern is formed. Thereafter, the wiring metal layer is etched by using the photoresist as an etching mask.
In recent semiconductor devices requiring finer patterns, however, resorting to only etching of the wiring metal layer causes a difficulty in production.
By way of example, therefore, there has been proposed a method of etching an insulating film formed in a region in which a wiring pattern should be formed, thereby forming a trench, embedding a wiring metal layer in the trench, and thereby forming a wiring layer (U.S. Pat. No. 4,944,836).
Furthermore, as a method developed from the above described method, there has been proposed a method of conducting formation of via holes for connecting underlying elements to a wiring layer in succession in a self-aligned manner, embedding a metal layer in the via holes and wiring trenches at the same time, and thereby forming via plugs and the wiring layer (U.S. Pat. No. 4,789,648). According to this method, processes can be shortened, and in addition failures due to pattern misalignment caused at the time of exposure of the via holes and the wiring trenches are suppressed. This method is called dual damascene method, and it has become a technique regarded as important in future semiconductor device manufacturing methods.
On the other hand, as different problems result upon fabrication of finer patterns, such as a lowering in signal transmission speed and occurrence of crosstalk caused by parasitic capacitance between adjacent wiring layers. As a countermeasure against these problems, a structure having an insulating film of a low permittivity between wiring layers is typically adopted. As such an insulating film of a low permittivity, a coated organic film, a coated inorganic film, a silicon oxide film containing fluorine, and an amorphous carbon film containing fluorine are being studied. In particular, the organic insulating film is extremely low in dielectric constant, and is a promising material.
Therefore, the above dual damascene method and the application of the organic insulating film are considered as necessary techniques in manufacture field of semiconductor device in the future.
FIG. 1 is a sectional view showing a conventional semiconductor device manufacturing method using a typical dual damascene method. On the surface of a Si substrate 300, a device isolation region 301 is formed. On the Si substrate 300, there are stacked in order a first etching stopper 302, a first interlayer insulating film 303, a second etching stopper 304, a second interlayer insulating film 305, and a photoresist 306 are stacked. A contact hole 307 is formed through a stacked body formed by them.
In this conventional manufacturing method using the dual damascene method, the contact hole 307 is formed by etching as described above, and thereafter exposure and etching of a photoresist (not shown) are conducted to form a wiring trench. For conducting the etching of the contact hole 307, it is necessary to conduct etching of the second interlayer insulating film 305, the second etching stopper 304, the first interlayer insulating film 303, and the first etching stopper 302 in order. In total, therefore, four etching processes are needed. In the case where the contact hole 307 is formed so as to extend to the device region and the device isolation region 301, as shown in FIG. 1, in a semiconductor device having high integration, the first etching stopper 302 functions to prevent a silicon oxide film in the device isolation region 301 from being etched.
For example, if silicon oxide films are used as the first and second interlayer insulating films 303 and 305 and silicon nitride films are used as the first and second etching stoppers 302 and 304, etching of the silicon oxide films is conducted, for example, by using CHF.sub.3 gas having a flow rate of 20 sccm and Ar gas having a flow rate of 580 sccm, setting the substrate temperature to 10.degree. C., and setting the bias power to 25 W. Furthermore, etching of the silicon nitride films is conducted, for example, by using CF.sub.4 gas having a flow rate of 20 sccm, H.sub.2 gas having a flow rate of 20 sccm, and Ar gas having a flow rate of 560 sccm, setting the substrate temperature to 10.degree. C., and setting the bias power to 25 W.
FIG. 2 is a sectional view showing a conventional semiconductor device manufacturing method using a dual damascene method disclosed in U.S. Pat. No. 4,789,648. On a Si substrate 401, there are stacked in order a first etching stopper 402, a first interlayer insulating film 403, and a second etching stopper 404. On the second etching stopper 404, a second interlayer insulating film 405 with a trench is provided. Furthermore, there is provided an anti-reflection coated film 408 embedded in the trench and covering the surface of a second interlayer insulating film 405. On the anti-reflection coated film 408, a patterned photoresist 406 is formed.
In this conventional manufacturing method using the dual damascene method, a fine pattern is formed in the photoresist by exposure for forming the contact hole. Therefore, preceding the contact hole, the wiring trench is formed as described above. Thereafter, the anti-reflection coated film 408 is embedded in the wiring trench, and flatting is conducted. Subsequently, the photoresist for forming the contact hole is subjected to exposure. When conducting etching to form the contact hole, this anti-reflection coated film 408 is also etched.
FIGS. 3A and 3B are sectional views showing a conventional semiconductor device manufacturing method using a dual damascene method disclosed in U.S. Pat. No. 4,944,836 in the order of process. As shown in FIG. 3A, a first etching stopper 501, a first interlayer insulating film 502, a patterned second etching stopper 503, a second interlayer insulating film 504, and a patterned photoresist 505 are stacked on a Si substrate 500 in order. Thereafter, wiring trenches 506 and a via hole 507 are formed as shown in FIG. 3B.
In this conventional manufacturing method using the dual damascene method, the photoresist 505 and the second etching stopper 503 are patterned. Therefore, the number of processes of etching for forming the wiring trench 506 and the via hole 507, i.e., contact-etching having a high aspect ratio is reduced. Furthermore, as compared with the above described two examples of the conventional technique, the contact hole can be formed more easily.
In the semiconductor device manufacturing method using the typical dual damascene method shown in FIG. 1, however, it is necessary to conduct over-etching as compared with the typical film thickness in the process of etching the silicon oxide film or the silicon nitride film, by taking the dispersion in the manufacture into consideration. At this time, etching in the lateral direction or deposition takes place. Therefore, it is extremely difficult to control the dimensions of the contact hole. Especially in such a dual damascene method, the film thickness etched to form the contact hole becomes the sum of the film thickness etched by using the conventional method and the film thickness of the insulating film. Therefore, the aspect ratio of the contact hole becomes extremely large. As a result, the etching of a fine contact hole is much more difficult.
In the semiconductor device manufacturing method using the dual damascene method shown in FIG. 2, the trench is formed previously before the exposure of the contact hole. In order to form a fine pattern by the exposure, however, it is necessary to embed the anti-reflection coated film in the trench and conduct flatting. In the contact hole etching process, therefore, an extra process of etching the anti-reflection coated film is needed. In addition, it is difficult to form a fine contact hole in this manufacturing method as well.
On the other hand, in the semiconductor device manufacturing method using the dual damascene method shown in FIGS. 3A and 3B, etching with a large number of processes is not required for forming the contact hole of high aspect ratio. As compared with the above described two examples of the conventional technique, therefore, the contact hole can be formed easily. However, it is necessary to make the etching rate of the second etching stopper equal to or less than one twentieth of the etching rate of the first interlayer insulating film and the second interlayer insulating film. If a film such as a silicon nitride film or a silicon oxide film is used, the control of the depth of the wiring trenches including a fine trench becomes extremely difficult. As a result, the margin in the manufacture is narrow and the yield is extremely low.